Application of the hottest CPLD in the on-line mon

2022-08-08
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Application of CPLD in circuit breaker monitoring data acquisition system

Abstract: This paper introduces the functional characteristics and hardware composition of circuit breaker monitoring data acquisition system, analyzes the advantages of using large-scale programmable logic device (CPLD) to realize the function expansion and logic control of the system, and discusses in detail how to use CPLD to realize chip selection, i/o and communication function expansion of CPU peripheral devices Expansion of mass storage. The results of logic simulation and hardware debugging show that CPLD can well realize the logic function of the system, and the logic design of the acquisition system is reasonable and feasible. The application of the device not only simplifies the circuit design, but also improves the reliability of the system. The system structure based on CPLD + CPU mode will be widely used in the field of power equipment monitoring

this paper introduces the circuit breaker monitoring data acquisition system based on the large-scale programmable logic device (CPLD) as the CPU coprocessor, which simplifies the hardware design of the system, improves the stability of the system, makes the system maintenance convenient, effectively realizes the parallel communication of data acquisition, storage and upload, and has the advantages of high functional integration and convenient programming

1 basic functions of circuit breaker monitoring data acquisition system

1.1 basic parameters of system monitoring [1]

a. monitor the breaking current of circuit breaker, and send it to the main CPU to predict the electrical life of circuit breaker contacts

b. monitor the bus voltage of the fault line

c. monitor the closing and opening coil current of the circuit breaker, and monitor the working conditions of the electromagnet, the controlled latch or valve and the interlocking contact during operation

d. monitor the closing and opening coil voltage of the circuit breaker, and monitor whether the control circuit and voltage are normal

e. monitor the opening/closing time and closing/opening position of circuit breaker

f. monitor the statistics of circuit breaker action times

g. monitor the starting times of the hydraulic or pneumatic mechanism, and estimate the oil or air leakage of the mechanism according to the recorded starting times

1.2 functions realized by the data acquisition system

the data acquisition system can realize storage, alarm, remote signaling, system self maintenance, network communication and expandable functions

2 system hardware working principle and structure block diagram

structure block diagram of data acquisition system is shown in Figure 1

the system is designed for CPU based on TMS320F206 (digital signal processing) chip of TI company. The chip adopts the improved Harvard structure, 30million pages of four-stage pipeline operation, and has 6 buses, which greatly improves the data processing capacity. Through the separation of program and data space, program instructions can be accessed at the same time, providing a high degree of parallelism. CPLD device is used as DSP coprocessor to complete DSP peripheral device expansion and logic control operation. DSP adopts external 32mhz crystal oscillator

2.1 peripheral device expansion

a. memory expansion. External global data memory (cy7c1021) 32 KB, occupying data space 8000h ~ ffffh. The local data memory is 64 kb, and the data storage space range is 0000H ~ ffffh. Access to external global or local data memory is determined through the/ds and/br pins of DSP through CPLD encoded output. The extended program memory 32 KB is used to store programs, occupying the program space of 0000H ~ 8000h. Extended nonvolatile memory ds1270ya/b is mass memory

b. multiplexing and a/d. The a/d conversion chip MAX125 is a high-speed, multi-channel data acquisition system chip with its own sampling and holding. With 14 bit conversion accuracy, the maximum sampling rate can reach 250 kbit/s, and the single channel conversion time is 3 μ s. It can meet the requirements of 100 sampling points per monitoring cycle. The double 4-out-2 multiplexer dg409 of Dallas company is selected as the multiplexer

c. extended clock core $936 with the mounting piece of these main equipment! HHE is used as the clock to record the working time of the system and calibrate the clock with the main processing board at fixed time

d. watchdog circuit. Use =lme? Chip n completes the system fault reset function

e. the Serial EEPROM expansion chip adopts at25640 chip to store the fixed value, and the fixed value can be adjusted

f. first in first out (fifp). The acquisition system and main processing system adopt parallel communication mode, and idt7202a chip is selected. It is based on first in first out, with internal dual port SRAM and internal read/write counter. Read/write operations are independent of each other, and synchronous and asynchronous communication can be carried out. It uses empty and full flag bits to prevent data underflow and overflow. Its capacity relaxation tester is mainly used to test the tensile stress relaxation mechanical properties of metal materials (such as steel strands, PC steel bars and steel wires) at room temperature, which is 1024 × 9 bit。

g. the communication interface part includes the communication between can and the main processing board, leaving RS-485 and RS-232 as communication standby interfaces

2.2 working principle of acquisition system

each data acquisition system corresponds to the data acquisition and processing of - channel analog quantity and 32 channel switching value input, with 64 channel switching value output at the same time. When the system works normally, 36 points are sampled in each cycle for analog power data, and 100 points are sampled in fault state

after the system initialization and self-test are completed, the internal timer of DSP can only enable the 4-piece multiplexer switch through CPLD at a fixed time. At the same time, the address is given, the multiplexer switch is gated, and the 8-way analog quantity is gated. Then, DSP gives a/d chip selection conversion signal through CPLD to start a/d conversion. The time interval for MAX125 to complete 32 restart must exceed 310 minutes; When the indoor temperature exceeds 25 ℃, the a/d conversion of analog quantity needs 96 μ s。 200 per sampling interval μ s. So the CPU uses the remaining 104 μ S completes data processing. The system generates fault handling interrupt through the fault start synchronization signal sy sent by the main CPU and other acquisition systems, the collected data of the system and the constant value comparison in the Serial EEPROM, and starts 100 point sampling. The data acquisition synchronization is realized through the synchronous acquisition signal sent by the main CPU. The sampling data is timely uploaded to the CPU of the main processing board through FIFO for data processing

cpu sends the switching value strobe signal to the switching value input board through CPLD, strobes each group of 16 channel switching value input, 64 channel switching value input is sent to the data bus through CPLD for 4 times, and is sent to the main processing board for data processing through FIFO after being processed by the acquisition board DSP

the switching value output sent by CPU is sent to the switching value output board through CPLD

main CPU and acquisition system pass 9/: timing calibration system

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